Exemplary embodiments of the present invention relate to semiconductor design technology, and more particularly, to a semiconductor memory for outputting strobe signals.
In general, a semiconductor memory device such as a double data rate synchronous DRAM (DDR SDRAM) generates a strobe signal in response to a column address strobe (CAS) signal (that is, a column command). The strobe signal is a pulse signal having a pulse width corresponding to an external clock signal. Such a strobe signal is used as a source signal in response to which main signals in column access are generated. The strobe signal is often used to generate a column selection signal, a write driver enable signal, and an input/output sense amplifying enable signal. Here, the column selection signal, the write driver enable signal, and the input/output sense amplifying enable signal may have a pulse width corresponding to the strobe signal.
According to an example, tCCD (that is, CAS to CAS Delay, which is a minimum time for accessing another column after accessing one column in the same bank) may be 2 tCK. Thus, the address information ADD is toggled at every 2 tCK. Considering the precharging time of the main/sub local input/output lines LIO and LIOb, the column selection signal YI is set to have a pulse width of 1 tCK. Thus, the strobe signal has the pulse width of 1 tCK. Since a skew may be generated for the address information ADD, the actual window for access of the address information ADD is less than 2 tCK. Therefore, an operation margin in light of such an access window is relatively small.
As a result, next address information ADD may unintentionally interfere when a voltage level difference between the main/sub local input/output lines LIO and LIOb is generated due to the data. Therefore, proper reading of data may be difficult.
Since a cycle of an external clock signal applied to a semiconductor memory device has been decreased to 1 nano second (ns), a pulse width of the strobe signal has also been reduced to 500 pico second (ps) to 1 nano second (ns). Accordingly, a pulse width of the column selection signal YI generated in response to the strobe signal also decreases. Time for generating a sufficient voltage level difference between the main/sub local input/output lines LIO and LIOb is not ensured. When the strobe signal has a relatively small pulse width, it may not swing fully to a desired level as a signal line for the strobe signal often has a large load. Therefore, the operation characteristic of a circuit may be deteriorated and an operation error may occur due to disappearance of the strobe signal.
In order to realize a high speed operation of a semiconductor device, a bank grouping mode to control tCCD as defined in specification has been used.
The bank grouping mode is a mode that groups a plurality of banks and when column access to a same bank of a group repeatedly occurs, tCCD (that is, Column Address Strobe (CAS) to CAS Delay) is extended. The bank grouping mode has been defined in specification to alleviate stress placed on semiconductor memory devices that operate at a speed higher than a certain speed.
More specifically, in a normal mode, tCCD is fixed to 2 tCK based on an external clock signal regardless of grouped banks. Thus, tCCD is 2 tCK for repeated column access to differently grouped banks during the normal mode. tCCD is also 2 tCK for repeated column access to a same group of banks during the normal mode. On the other hand, during the bank grouping mode, tCCD is 2 tCK for repeated column access to differently grouped banks and larger than 2 tCK (for example, 3 tCK or 4 tCK) for repeated column access within in a same bank group.
FIG. 1 is a table illustrating grouping of banks in a bank grouping mode. The table shows bank addresses BA0, BA1, BA2, and BA3, and grouped bank states of a semiconductor memory device having a 512-mega 8-bank structure, a 1-giga 16-bank structure, and a 2-giga 16-bank structure.
Referring to FIG. 1, in case of the semiconductor memory device having the 512-mega 8-bank structure, a 0th bank and a first bank are defined as a first bank group, a second bank and a third bank are defined as a second bank group, a fourth bank and a fifth bank are defined as a third bank group, and a sixth bank and a seventh bank are defined as a fourth bank group.
In case of the semiconductor memory device having the 1-giga 16-bank structure, a 0th bank to a third bank are defined as a first bank group, a fourth bank to a seventh bank are defined as a second bank group, an eighth bank to an eleventh bank are defined as a third bank group, and a twelfth bank to a fifteenth bank are defined as a fourth bank group.
In case of the semiconductor memory device having a 2-giga 16-bank structure, each of four consecutive banks are defined as a first bank group, a second bank group, a third bank group, and a fourth group bank similar to the semiconductor memory device having the 1-giga 16-bank structure.
For illustration purposes, the exemplary embodiments of the present subject matter will be described in reference to a 1-giga 16-bank semiconductor memory device.
For example, in case of a normal mode, if columns in the first bank group are accessed, columns in the first to fourth bank groups are accessed after 2 tCK regardless of which banks. In other words, 2 tCK is required to access a bank in the first to fourth bank groups after accessing another bank in the first to fourth bank groups. Thus, tCCD is always equivalent to 2 tCK regardless of groups of banks.
In case of a bank grouping mode, 4 tCK is required to access a column in a first bank group after a column in the first group are accessed. On the other hand, 2 tCK is required to access a column in any one of the second to fourth bank groups after accessing a column in the first bank group. That is, if columns are repeatedly accessed within a same one of grouped banks, tCCD is 4 tCK. If column access switches to different ones of the grouped banks, tCCD is 2 tCK.
FIGS. 2A and 2B are diagrams illustrating bank access sequence in the bank grouping mode based on specification. FIG. 2A shows a waveform in a normal mode, and FIG. 2B shows a waveform in a bank grouping mode. In FIGS. 2A and 2B, A is a first bank signal, B is a second bank signal, C is a third bank signal, and D is a fourth bank signal.
Referring to FIGS. 2A and 2B, in case of a typical semiconductor memory device, when a column address strobe signal CAS is activated for accessing columns in a corresponding bank, data information (DQ) is applied to an input/output bus (IO BUS).
In case of a normal mode in FIG. 2A, regardless of which one of grouped banks is accessed, the column address strobe signal CAS is applied at 2 tCK based on a cycle of an external clock signal CLK_EXT. Thus, data information corresponding to the first bank group is applied to the input/output but (IO BUS) at an interval of 2 tCK, and data information corresponding to the second to fourth bank groups are also applied to the input/output bus (IO BUS) at an interval of 2 tCK. Thus, data information is toggled at an interval of 2 tCK.
However, in the case of a bank grouping mode of FIG. 2B, the column address strobe signal CAS is applied at an interval of 2 tCK in column access to differently grouped banks. The column address strobe signal CAS is applied at an interval of 4 tCK in repeated column access in a same grouped bank. Thus, if data information corresponding to the first bank group is applied to the input/output bus (IO BUS), subsequent data information corresponding to the second to fourth bank groups can be applied after 2 tCK, and data information corresponding to the same first bank group can be applied after 4 tCK. Operations for the second to fourth bank groups are similar to those described above the first bank group. Here, even when column address strobe signal is toggled at an interval of 4 tCK, data information is toggled at an interval of 2 tCK at the input/output bus (IO BUS). This means that the bank grouping mode and the normal mode have the same input/output bus efficiency.
FIG. 3 is a conventional strobe signal generating device showing banks grouped into 4 groups.
Referring to FIG. 3, when a plurality of banks are grouped into 4 groups, the conventional strobe signal generating device includes a column address strobe pulse generating unit 301, a first strobe signal generating unit 302, a second strobe signal generating unit 303, a third strobe signal generating unit 304 and a fourth strobe signal generating unit 305.
The column address strobe pulse generating unit 301 is configured to receive a column bank signal CBK<2:3>, a column address strobe signal CASP and a bank grouping signal GROUP and output a column address strobe pulse signal CASP8<0:3>.
The first strobe signal generating unit 302 is configured to receive a first column address strobe pulse signal CASP8<0> from the column address strobe pulse generating unit 301 and the column bank signal CBK<0:1> and output first to fourth strobe signals STROBE<0:3> of a first group 306. The second strobe signal generating unit 303 is configured to receive a second column address strobe pulse signal CASP8<1> from the column address strobe pulse generating unit 301 and the column bank signal CBK<0:1> and output fifth to eighth strobe signals STROBE<4:7> of a second group 307.
The third strobe signal generating unit 304 is configured to receive a third column address strobe pulse signal CASP8<2> from the column address strobe pulse generating unit 301 and the column bank signal CBK<0:1> and output ninth to twelfth strobe signals STROBE<8:11> of a third group 308. The fourth strobe signal generating unit 305 is configured to receive a fourth column address strobe pulse signal CASP8<3> from the column address strobe pulse generating unit 301 and the column bank signal CBK<0:1> and output thirteenth to sixteenth strobe signals STROBE<12:15> of a fourth group 309.
The bank grouping signal GROUP is outputted from a mode register set MRS block and is a signal which is enabled during the bank group mode.
That is, when the banks are grouped into 4 groups, 4 column address strobe pulse signals CASP8<0, 1, 2, 3> are inputted into the first to fourth strobe signal generating units 302 to 305, respectively. The number of column address strobe pulse signals is the same as the number of groups.
FIG. 4 is a conventional strobe signal generating device when the banks are grouped into 8 groups.
Referring to FIG. 4, when a plurality of banks are grouped into 8 groups, the conventional strobe signal generating device includes a column address strobe pulse generating unit 401, a first strobe signal generating unit 402, a second strobe signal generating unit 403, a third strobe signal generating unit 404, a fourth strobe signal generating unit 405, a fifth strobe signal generating unit 406, a sixth strobe signal generating unit 407, a seventh strobe signal generating unit 408 and an eighth strobe signal generating unit 409.
The column address strobe pulse generating unit 401 is configured to receive a column bank signal CBK<1:3>, a column address strobe signal CASP and a bank grouping signal GROUP and output a column address strobe pulse signal CASP8<0:8>.
The first strobe signal generating unit 402 is configured to receive a first column address strobe pulse signal CASP8<0> from the column address strobe pulse generating unit 401 and the column bank signal CBK<0> and output first and second strobe signals STROBE<0:1> of a first group 410. The second strobe signal generating unit 403 is configured to receive a second column address strobe pulse signal CASP8<1> from the column address strobe pulse generating unit 401 and the column bank signal CBK<0> and output third and fourth strobe signals STROBE<2:3> of a second group 411.
The third strobe signal generating unit 404 is configured to receive a third column address strobe pulse signal CASP8<2> from the column address strobe pulse generating unit 401 and the column bank signal CBK<0> and output fifth and sixth strobe signals STROBE<4:5> of a third group 412. The fourth strobe signal generating unit 405 is configured to receive a fourth column address strobe pulse signal CASP8<3> from the column address strobe pulse generating unit 401 and the column bank signal CBK<0> and output seventh and eighth strobe signals STROBE<6:7> of a fourth group 413.
The fifth strobe signal generating unit 406 is configured to receive a fifth column address strobe pulse signal CASP8<4> from the column address strobe pulse generating unit 401 and the column bank signal CBK<0> and output ninth and tenth strobe signals STROBE<8:9> of a fifth group 414. The sixth strobe signal generating unit 407 is configured to receive a sixth column address strobe pulse signal CASP8<5> from the column address strobe pulse generating unit 401 and the column bank signal CBK<0> and output eleventh and twelfth strobe signals STROBE<10:11> of a sixth group 415.
The seventh strobe signal generating unit 408 is configured to receive a seventh column address strobe pulse signal CASP8<6> from the column address strobe pulse generating unit 401 and the column bank signal CBK<0> and output thirteenth and fourteenth strobe signals STROBE<12:13> of a seventh group 416. The eighth strobe signal generating unit 409 is configured to receive a eighth column address strobe pulse signal CASP8<7> from the column address strobe pulse generating unit 401 and the column bank signal CBK<0> and output fifteenth and sixteenth strobe signals STROBE<14:15> of a eighth group 417.
That is, when the banks are grouped into 8 groups, 8 column address strobe pulse signals CASP8<0:7> are inputted into the first to eighth strobe signal generating units 402 to 409, respectively. The number of column address strobe pulse signals is the same as the number of groups.
FIG. 5 is a detailed diagram of the column address strobe pulse generating unit shown in FIG. 4.
Referring to FIG. 5, the column address strobe pulse generating unit 401 includes decoder 50 and first to eighth pulse generators 51 to 58.
The decoder 50 is configured to receive 3-bit column bank signal CBK<1:3> and output 8 bank signals BA<0> to BA<7>. Each of the first to eighth pulse generators 51 to 58 is configured to receive the column address strobe signal CASP, the bank grouping signal GROUP and the corresponding bank signal among the 8 bank signals BA<0> to BA<7>, and output the column address strobe pulse signal corresponding to the bank signal among the 8 column address strobe pulse signals CASP8<0> to CASP8<7>.
As described above, when 16 banks are grouped into 4 groups, 4 column address strobe pulse signals is required to output 16 strobe signals. When 16 banks are grouped into 8 groups, 8 column address strobe pulse signals is required to output 16 strobe signals. Therefore, the number of lines connected to each bank of the 8-group case is two times than that of the 4-group case.